test_code/CHERY_EMB_GHS/ld/dr7f701374.ld

/*===========================================================================*/
/* Module       = dr7f701374.ld                                              */
/* Version      = V1.21                                                      */
/*                extracted from device file dr7f701373.dvf                  */
/*                by DeFiXRH850 0.9.1.0                                      */
/*===========================================================================*/
/*                                  COPYRIGHT                                */
/*===========================================================================*/
/* Copyright (c) 2017 by Renesas Electronics Europe GmbH,                    */
/*               a company of the Renesas Electronics Corporation            */
/*===========================================================================*/
/* Purpose:     Template of linker directive file                            */
/*                                                                           */
/*===========================================================================*/
/*                                                                           */
/* Warranty Disclaimer                                                       */
/*                                                                           */
/* Because the Product(s) is licensed free of charge, there is no warranty   */
/* of any kind whatsoever and expressly disclaimed and excluded by Renesas,  */
/* either expressed or implied, including but not limited to those for       */
/* non-infringement of intellectual property, merchantability and/or         */
/* fitness for the particular purpose.                                       */
/* Renesas shall not have any obligation to maintain, service or provide bug */
/* fixes for the supplied Product(s) and/or the Application.                 */
/*                                                                           */
/* Each User is solely responsible for determining the appropriateness of    */
/* using the Product(s) and assumes all risks associated with its exercise   */
/* of rights under this Agreement, including, but not limited to the risks   */
/* and costs of program errors, compliance with applicable laws, damage to   */
/* or loss of data, programs or equipment, and unavailability or             */
/* interruption of operations.                                               */
/*                                                                           */
/* Limitation of Liability                                                   */
/*                                                                           */
/* In no event shall Renesas be liable to the User for any incidental,       */
/* consequential, indirect, or punitive damage (including but not limited    */
/* to lost profits) regardless of whether such liability is based on breach  */
/* of contract, tort, strict liability, breach of warranties, failure of     */
/* essential purpose or otherwise and even if advised of the possibility of  */
/* such damages. Renesas shall not be liable for any services or products    */
/* provided by third party vendors, developers or consultants identified or  */
/* referred to the User by Renesas in connection with the Product(s) and/or  */
/* the Application.                                                          */
/*                                                                           */
/*===========================================================================*/
/* Environment:                                                              */
/*              Device:         R7F701373xABG                                */
/*              IDE:            GHS Multi for V800  V6.xx or later           */
/*===========================================================================*/
MEMORY
 {
/*  iROM_APP         : ORIGIN = 0x00000000,  LENGTH = 2M -256K  //BOOT used*/
/*  iROM_APP         : ORIGIN = 0x00000000,  LENGTH = 2M                   */
  iROM_APP         : ORIGIN = 0x00000000,  LENGTH = 2M

  /* ------------------------------------------------------------------------ */
  /*                            Local RAM                                     */
  /* ------------------------------------------------------------------------ */
  LR_PE1     : ORIGIN = 0xFEBE0000,  LENGTH = 128K
//  LR_PE1     : ORIGIN = 0xFEBE0000,  LENGTH = 100K
  LR_PE1_TOP : ORIGIN = .         ,  LENGTH = 0
//  VX1000_A0  : ORIGIN = 0xFEEF9000,  LENGTH = 28K
// VX1000_TOP : ORIGIN = .         ,  LENGTH = 0
  /* ------------------------------------------------------------------------ */
  /*                            Global RAM                                    */
  /* ------------------------------------------------------------------------ */
/*  GRA        : ORIGIN = 0xFEED8000,  LENGTH = 148K
//  GRA_TOP    : ORIGIN = .         ,  LENGTH = 0
  VX1000_A0  : ORIGIN = 0xFEEFD000,  LENGTH = 12K
  VX1000_TOP : ORIGIN = .         ,  LENGTH = 0
 
  GRB        : ORIGIN = 0xFEF00000,  LENGTH = 160K
  GRA_TOP    : ORIGIN = .         ,  LENGTH = 0
*/
  /* ------------------------------------------------------------------------ */
  /*                            Global RAM                                    */
  /* ------------------------------------------------------------------------ */
  GRA        : ORIGIN = 0xFEED8000,  LENGTH = 300K
  GRA_TOP    : ORIGIN = .         ,  LENGTH = 0
  VX1000_A0  : ORIGIN = 0xFEF23000,  LENGTH = 20K
  VX1000_TOP : ORIGIN = .         ,  LENGTH = 0
 
  /* ------------------------------------------------------------------------ */
  /*                                Stack                                     */
  /* ------------------------------------------------------------------------ */
  STACK      : ORIGIN = 0xFEDFF800,  LENGTH = 2K
  STACK_TOP  : ORIGIN = .         ,  LENGTH = 0
 }

SECTIONS
 {
/* Start of internal ROM area (CFUAA) */
/* .intvect 0x00000          align(16)            :> iROM_APP  */
/* .intvect 0x0000          align(16)            :> iROM_APP  */
  .intvect 0x0000          align(16)            :> iROM_APP   /* start of interrupt vector. This section contains RESET and exception table for PE0 */
  .inttable                align(0x200)         :>.
  .inttable_end                                 :>.

  .OS_EXCVEC align(512):
  {
	  _OS_EXCVEC_OSCORE0_CODE_START = .;
	  *(.OS_EXCVEC_OSCORE0)     /* Startup code */
	  _OS_EXCVEC_OSCORE0_CODE_END = .;
	  . = align(512);
  } >.

  .rozdata                              :>.      /* constant datas in ZDA area */
  .robase   align(4)                    :>.      /* initialize textpointer TP for SDA addressing */
  .rosdata  align(4)                    :>.      /* constant datas in SDA area */
  .rodata   align(4)                    :>.      /* constant datas in normal area */
  .multicore_init                       :>.

  .CONST_ROM_1BIT                               :>.  
  .CONST_ROM_8BIT                               :>.
  .CONST_ROM_16BIT                              :>.
  .CONST_ROM_32BIT                              :>.
  .CONST_ROM_UNSPECIFIED                        :>.

  .CONST_FAR_ROM_1BIT                           :>.
  .CONST_FAR_ROM_8BIT                           :>.
  .CONST_FAR_ROM_16BIT                          :>.
  .CONST_FAR_ROM_32BIT                          :>.
  .CONST_FAR_ROM_UNSPECIFIED                    :>.

  .ADC_CFG_DATA_UNSPECIFIED             :>.
  .DIO_CFG_DATA_UNSPECIFIED             :>.
  .PORT_CFG_DATA_UNSPECIFIED            :>.
  .ICU_CFG_DATA_UNSPECIFIED             :>.
  .ICU_CFG_DBTOC_UNSPECIFIED            :>.
  .SPI_CFG_DBTOC_UNSPECIFIED      align(4)      :>.
  .SPI_CFG_DATA_8BIT                            :>.
  .SPI_CFG_DATA_16BIT             align(4)      :>.
  .SPI_CFG_DATA_UNSPECIFIED       align(4)      :>.
  .GPT_CFG_DATA_UNSPECIFIED             :>.
  .FLS_CFG_DATA_UNSPECIFIED             :>.

  .DEFAULT_CODE_ROM                     :>.


  /* program code area */
  .text     align(4)                    :>.
  
  .ADC_PUBLIC_CODE_ROM                  :>.
  .ADC_PRIVATE_CODE_ROM                 :>.
  .ADC_FAST_CODE_ROM                    :>.
  .ADC_APPL_CODE_ROM                    :>.
  .MCU_APPL_CODE_ROM                    :>.
  .MCU_PRIVATE_CODE_ROM                 :>.
  .MCU_PUBLIC_CODE_ROM                  :>.
  .MCU_FAST_CODE_ROM                    :>.
  .PORT_PUBLIC_CODE_ROM                 :>.
  .PORT_PRIVATE_CODE_ROM                :>.
  .DIO_PUBLIC_CODE_ROM                  :>.
  .DIO_APPL_CODE_ROM                    :>.
  .SPI_PUBLIC_CODE_ROM                  :>.
  .SPI_PRIVATE_CODE_ROM                 :>.
  .SPI_APPL_CODE_ROM                    :>.
  .SPI_FAST_CODE_ROM                    :>.
  .GPT_PUBLIC_CODE_ROM                  :>.
  .GPT_PRIVATE_CODE_ROM                 :>.
  .GPT_APPL_CODE_ROM                    :>.
  .GPT_FAST_CODE_ROM                    :>. 
  .ICU_PUBLIC_CODE_ROM                  :>.
  .ICU_PRIVATE_CODE_ROM                 :>.
  .ICU_APPL_CODE_ROM                    :>.
  .ICU_FAST_CODE_ROM                    :>.
  .PWM_PUBLIC_CODE_ROM                  :>.
  .PWM_PRIVATE_CODE_ROM                 :>.
  .PWM_APPL_CODE_ROM                    :>.
  .PWM_FAST_CODE_ROM                    :>.
  .FLS_SAMPLE_CODE_ROM                  :>.
  .FLS_PUBLIC_CODE_ROM                  :>.
  .FLS_PRIVATE_CODE_ROM                 :>.
  .FLS_APPL_CODE_ROM                    :>.
  .WDG_PUBLIC_CODE_ROM                  :>.
  .WDG_PRIVATE_CODE_ROM                 :>.
  .WDG_FAST_CODE_ROM                    :>.
  .WDG59_A_APPL_CODE_ROM                :>.
  .WDG59_B_APPL_CODE_ROM                :>.
  .OS_CODE                              :>.
  .OS_CONST                             :>.
  .OS_APPL_CONST                        :>.

  .fixaddr  align(4)                    :>.      /* ghs internal (compiler) */
  .fixtype  align(4)                    :>.      /* ghs internal (compiler) */
  .secinfo  align(4)                    :>.      /* ghs internal (runtime library) */
  .syscall  align(4)                    :>.      /* ghs internal (linker) */

  .romdata  ROM(.data)                  :>.      /* constant data to initialize variables (copied to RAM at startup)*/
  .romzdata ROM(.zdata)                 :>.      /* constant data to initialize variables in ZDA area (copied to RAM at startup)*/
  .romsdata ROM(.sdata)                 :>.      /* constant data to initialize variables in SDA area (copied to RAM at startup)*/
  .romtdata ROM(.tdata)                 :>.      /* constant data to initialize variables in TDA area (copied to RAM at startup)*/
  .romsldata ROM(.sldata)               :>.      /* constant data to initialize variables in LSDA area (copied to GRAM at startup)*/

  .ROM.RAM_1BIT         ROM(.RAM_1BIT)          :>.  
  .ROM.RAM_8BIT         ROM(.RAM_8BIT)          :>.
  .ROM.RAM_16BIT        ROM(.RAM_16BIT)         :>.
  .ROM.RAM_32BIT        ROM(.RAM_32BIT)         :>.
  .ROM.RAM_UNSPECIFIED  ROM(.RAM_UNSPECIFIED)   :>.
  .ROM.FAST_RAM_1BIT         ROM(.FAST_RAM_1BIT)          :>.
  .ROM.FAST_RAM_8BIT         ROM(.FAST_RAM_8BIT)          :>.
  .ROM.FAST_RAM_16BIT        ROM(.FAST_RAM_16BIT)         :>.
  .ROM.FAST_RAM_32BIT        ROM(.FAST_RAM_32BIT)         :>.
  .ROM.FAST_RAM_UNSPECIFIED  ROM(.FAST_RAM_UNSPECIFIED)   :>.
  .ROM.OS_INITVAR_OSCORE0  ROM(.OS_INITVAR_OSCORE0)   :>.

   /*PE1 local ram*/
  .OS_INITVAR_OSCORE0                           :>LR_PE1
  .OS_VAR_OSCORE0                               :>.
  .OS_STACK_OSCORE0                             :>.

 /* Start of internal RAM area (GRA) */
  .data                        align(4)         :> GRA   /* initialized data */
  .sdabase                     align(4)         :>.      /* initialize global pointer GP for SDA addressing */
  .zdata                       align(4)         :>.      /* initialized data in ZDA area */
  .sldata                      align(4)         :>.      /* initialized data in LSDA area */
  .sdata                       align(4)         :>.      /* initialized data in SDA area */
  .RAM_1BIT                    NOCLEAR          :>.      /* initialized data in SDA area */
  .RAM_8BIT                    NOCLEAR          :>.      /* initialized data in SDA area */
  .RAM_16BIT                   NOCLEAR align(4) :>.      /* initialized data in SDA area */
  .RAM_32BIT                   NOCLEAR align(4) :>.      /* initialized data in SDA area */
  .RAM_UNSPECIFIED             NOCLEAR align(4) :>.      /* initialized data in SDA area */
  .FAST_RAM_1BIT               NOCLEAR          :>.      /* initialized data in SDA area */
  .FAST_RAM_8BIT               NOCLEAR          :>.      /* initialized data in SDA area */
  .FAST_RAM_16BIT              NOCLEAR align(4) :>.      /* initialized data in SDA area */
  .FAST_RAM_32BIT              NOCLEAR align(4) :>.      /* initialized data in SDA area */
  .FAST_RAM_UNSPECIFIED        NOCLEAR align(4) :>.      /* initialized data in SDA area */

  .bss                         align(4)         :>.      /* zero initialized data */
  .zbss                        align(4)         :>.      /* zero initialized data in ZDA area */
  .slbss                       align(4)         :>.      /* zero initialized data in LSDA area */
  .sbss                        align(4)         :>.      /* zero initialized data in SDA area */
  .NOINIT_RAM_1BIT             NOCLEAR          :>.      /* no initialized data in SDA area */
  .NOINIT_RAM_8BIT             NOCLEAR          :>.      /* no initialized data in SDA area */
  .NOINIT_RAM_16BIT            NOCLEAR align(4) :>.      /* no initialized data in SDA area */
  .NOINIT_RAM_32BIT            NOCLEAR align(4) :>.      /* no initialized data in SDA area */
  .NOINIT_RAM_UNSPECIFIED      NOCLEAR align(4) :>.      /* no initialized data in SDA area */
  .NOINIT_RAM_PTR              NOCLEAR align(4) :>.      /* no initialized data in SDA area */
  .NOINIT_RAM_64BIT            NOCLEAR align(8) :>.      /* no initialized data in SDA area */
  .OS_GLOBAL_NOCACHE_VAR                        :>.

  
  /* Renesas FDL/EEL data sections */
  .R_FDL_Data                           :>.      /* FDL data */
  .R_FDL_CodeRam                        :>.      /* FDL code in RAM (Empty if R_FDL_EXE_INIT_CODE_ON_STACK is defined) */
  .R_EEL_Data                           :>.      /* EEL data (Empty if no EEL is implemented) */

  .R_FAL_DATA           align(4)        :>.      /* FAL data */
  .R_FAL_CODE_USR       align(4)        :>.      /* User code located in RAM */
  .R_FAL_CODE_RAM       align(4)        :>.      /* FAL code in RAM */
  .R_FAL_CODE_RAM_EX_PROT  pad(0x50) align(4):>. /* Blank section after FAL code to avoid pre-fetch ECC errors*/

  .ADC_CFG_RAM_UNSPECIFIED       NOCLEAR       :>.
  .ICU_CFG_RAM_UNSPECIFIED       NOCLEAR       :>.
  
  .FLS_USER_BUFFER_CODE_RAM    align(4) :>.      /* Application Buffer  */
  .FLS_PRIVATE_CODE_RAM                 :>.

  .ramtext  align(128)  MAX_SIZE(0x2000)        :>.      /* initialized and zero-initialized data in TDA area */
  .tdata    align(4)    MAX_SIZE(0x0100)        :>.      /* initialized and zero-initialized data in TDA area */
  .exec     align(128)                          :>.
  .mev_address                 align(32)        :>.      /* Mutual Exclusive Variable is used for Sync flags between multi core */

  .heapbase align(4)                            :>.
  .heap     align(4)
            pad(addr(GRA_TOP)-addr(.heapbase))
            NOCLEAR                             :>.      /* definition of heap size */
  .top_of_RAM           align(4)                :> GRA_TOP

  .gvx1000_data_AEAR align(4):
  {
	  _gvx1000_data_AEAR_START = .;
	  *(.gvx1000_data)     /* gvx1000 code data */
	  _gvx1000_data_AEAR_END = .;
	  . = align(4);
  } >VX1000_A0
  

  .stack    align(4)    pad(0x0800)             :> STACK      /* definition of stack size */

  /*  Symbols for compiler references */

 }

/*===========================================================================*/
/*      End of File                                                          */
/*===========================================================================*/